module Hazard(PCWrite, IFWrite, Bubble, Branch, ALUZero4, Jump, rw, rw3, rw4 ,rw5, rs, rt, Reset_L, CLK);

	input			Branch;
	input			ALUZero4;	
	input			Jump;
	input 	[4:0]	rw3, rw4 ,rw5;
	
	input	[4:0]	rw;
	input	[4:0]	rs;
	input	[4:0]	rt;
		
	input			Reset_L;
	input			CLK;
	
	output		PCWrite;
	output		IFWrite;
	output		Bubble;
	
	reg		PCWrite;
	reg		IFWrite;
	reg		Bubble;
	
	/*initial begin
		PCWrite <= 1;
		PCWrite <= 1;
	end*/
	
	always @ (negedge CLK) begin
	
	if(~Reset_L) begin
			PCWrite <= 0;
			IFWrite <= 0;
			Bubble <= 0;
	end
	
	if(Jump) begin
		 #2 PCWrite <= 0;
		 #1 IFWrite <= 0;
	end
		else if(~Jump) begin
		#1 IFWrite <=1;
	end
	
	if(Branch) begin
		 #4 PCWrite <= 0;
		// #1 IFWrite <= 0;
	end
	else if(~Branch) begin
		#1 PCWrite <=1;
	end
	
/*	if(rs==rw5 || rt==rw5 && rw5!=0) begin
		Bubble <= 1;
	end
	else begin Bubble <= 0; end
*/	


/*	
	if find register that is being written for the past three instructions and find out if the current instruction needs any of these registers
		then bubble <= 1;
		else bubble <= 0;
	
	if branch instruction is decoded then PCWrite <= 0 for the next two clock cycles. & IFWrite <= 0 for an additional clock cycle
	
	if jump then PCWrite <=0 for a single cycle & IFWrite <= 0 for an additional clock cycle
	
	if branch is not taken then IFWrite is not written to.
	
	IFWrite <= 1 when jump is succesfully taken.
	*/
end
endmodule
